How Many Clock Cycles to Read From Disk

Clock Cycles

Sequential Logic Design

Sarah 50. Harris , David Harris , in Digital Design and Computer Architecture, 2022

3.5.ii System Timing

The clock menstruum or wheel time, T _c , is the time betwixt rising edges of a repetitive clock signal. Its reciprocal, f _c = 1/T _c , is the clock frequency. All else being the same, increasing the clock frequency increases the piece of work that a digital system tin attain per unit of measurement time. Frequency is measured in units of Hertz (Hz), or cycles per second: 1 megahertz (MHz) = 10⁶ Hz, and 1 gigahertz (GHz) = 10⁹ Hz.

In the three decades from when 1 of the authors' families bought an Apple 2+ estimator to the present time of writing, microprocessor clock frequencies accept increased from ane   MHz to several GHz, a factor of more than than 1000. This speedup partially explains the revolutionary changes computers take made in society.

Figure 3.38(a) illustrates a generic path in a synchronous sequential circuit whose clock flow we wish to calculate. On the rising edge of the clock, annals R1 produces output (or outputs) Q1. These signals enter a block of combinational logic, producing D2, the input (or inputs) to register R2. The timing diagram in Figure three.38(b) shows that each output signal may outset to alter a contamination delay afterward its input changes and settles to the final value within a propagation delay after its input settles. The grayness arrows represent the contamination delay through R1 and the combinational logic, and the blue arrows correspond the propagation delay through R1 and the combinational logic. We analyze the timing constraints with respect to the setup and hold fourth dimension of the second annals, R2.

Figure 3.38. Path between registers and timing diagram

Setup Time Constraint

Figure iii.39 is the timing diagram showing merely the maximum delay through the path, indicated by the blue arrows. To satisfy the setup time of R2, D2 must settle no later than the setup time before the next clock edge. Hence, we find an equation for the minimum clock flow:

Figure 3.39. Maximum filibuster for setup time constraint

(3.13) $T_c\ge t_{\mathit{pcq}}+t_{\mathit{pd}}+t_{\text{setup}}$

In commercial designs, the clock period is often dictated by the Managing director of Engineering or by the marketing department (to ensure a competitive production). Moreover, the flip-flop clock-to-Q propagation filibuster and setup fourth dimension, t _pcq and t _setup, are specified by the manufacturer. Hence, we rearrange Equation iii.thirteen to solve for the maximum propagation delay through the combinational logic, which is usually the only variable under the control of the private designer.

(iii.14) $t_{\mathit{pd}}\le T_c-(t_{\mathit{pcq}}+t_{\text{setup}})$

The term in parentheses, t _pcq + t _setup, is chosen the sequencing overhead. Ideally, the unabridged cycle time T _c would be available for useful computation in the combinational logic, t _pd . Nevertheless, the sequencing overhead of the flip-flop cuts into this fourth dimension. Equation 3.14 is called the setup time constraint or max-delay constraint because it depends on the setup fourth dimension and limits the maximum delay through combinational logic.

If the propagation delay through the combinational logic is as well great, D2 may not have settled to its terminal value past the time R2 needs information technology to exist stable and samples it. Hence, R2 may sample an wrong result or fifty-fifty an illegal logic level, a level in the forbidden region. In such a case, the circuit will malfunction. The problem can exist solved by increasing the clock menses or by redesigning the combinational logic to have a shorter propagation delay.

Concord Fourth dimension Constraint

The register R2 in Figure 3.38(a) also has a hold time constraint. Its input, Dii, must not change until some time, t _hold, later on the rising edge of the clock. According to Figure three.40, D2 might modify as soon as t _ccq + t _cd later on the ascension edge of the clock. Hence, we find

Figure 3.40. Minimum delay for hold time constraint

(3.15) $t_{\mathit{ccq}}+t_{\mathit{cd}}\ge t_{\text{hold}}$

Again, t _ccq and t _concord are characteristics of the flip-flop that are usually outside the designer's control. Rearranging, we tin solve for the minimum contamination filibuster through the combinational logic:

(3.16) $t_{\mathit{cd}}\ge t_{\text{agree}}-t_{\mathit{ccq}}$

Equation 3.16 is chosen the concur fourth dimension constraint or min-delay constraint considering it limits the minimum delay through combinational logic.

We take causeless that any logic elements can be continued to each other without introducing timing problems. In particular, nosotros would wait that two flip-flops may be straight cascaded as in Figure iii.41 without causing concord time problems.

Effigy 3.41. Back-to-back flip-flops

In such a instance, t _cd = 0 because in that location is no combinational logic between flip-flops. Substituting into Equation 3.16 yields the requirement that

(3.17) $t_{\text{concur}}\le t_{\mathit{ccq}}$

In other words, a reliable flip-flop must have a hold time shorter than its contamination delay. Often, flip-flops are designed with t _hold = 0 then that Equation 3.17 is always satisfied. Unless noted otherwise, we will usually brand that supposition and ignore the agree time constraint in this book.

Nevertheless, hold time constraints are critically of import. If they are violated, the just solution is to increase the contamination delay through the logic, which requires redesigning the circuit. Unlike setup time constraints, they cannot be stock-still by adjusting the clock menses. Redesigning an integrated excursion and manufacturing the corrected blueprint takes months and millions of dollars in today's avant-garde technologies, so hold time violations must be taken extremely seriously.

Putting Information technology All Together

Sequential circuits have setup and hold time constraints that dictate the maximum and minimum delays of the combinational logic between flip-flops. Mod flip-flops are normally designed then that the minimum filibuster through the combinational logic tin be 0—that is, flip-flops can be placed back-to-dorsum. The maximum delay constraint limits the number of consecutive gates on the critical path of a high-speed excursion because a high clock frequency means a curt clock period.

Example three.10

Timing Analysis

Ben Bitdiddle designed the excursion in Figure iii.42. According to the data sheets for the components he is using, flip-flops take a clock-to-Q contagion delay of 30 ps and a propagation delay of 80 ps. They have a setup time of fifty ps and a concur time of lx ps. Each logic gate has a propagation filibuster of 40 ps and a contamination delay of 25 ps. Assistance Ben decide the maximum clock frequency and whether any hold time violations could occur. This procedure is called timing analysis.

Effigy three.42. Sample excursion for timing assay

Solution

Figure 3.43(a) shows waveforms illustrating when the signals might change. The inputs, A to D, are registered, and so they just change shortly after CLK rises.

Figure three.43. Timing diagram: (a) general case, (b) critical path, (c) short path

The critical path occurs when B = 1, C = 0, D = 0, and A rises from 0 to 1, triggering n1 to rise, X′ to rise, and Y′ to fall, equally shown in Effigy 3.43(b). This path involves three gate delays. For the critical path, we assume that each gate requires its total propagation delay. Y′ must fix before the next rising edge of the CLK. Hence, the minimum wheel time is

(3.18) $T_c\ge t_{\mathit{pcq}}+3t_{\mathit{pd}}+t_{\text{setup}}=80+\mathrm{three}\times \mathrm{forty}+\mathrm{l}=250\text{ps}$

The maximum clock frequency is f _c = 1/T _c = 4   GHz.

A brusque path occurs when A = 0 and C rises, causing X′ to rise, as shown in Figure 3.43(c). For the short path, nosotros assume that each gate switches subsequently merely a contamination delay. This path involves but one gate delay, so it may occur subsequently t _ccq + t _cd = 30 + 25 = 55   ps. But recollect that the flip-flop has a agree time of 60 ps, meaning that 10′ must remain stable for 60 ps after the rising border of CLK for the flip-flop to reliably sample its value. In this case, 10′ = 0 at the first rising edge of CLK, and so we want the flip-bomb to capture X = 0. Considering 10′ did not hold stable long plenty, the actual value of X is unpredictable. The circuit has a agree time violation and may behave erratically at any clock frequency.

Instance iii.11

Fixing Hold Fourth dimension Violations

Alyssa P. Hacker proposes to gear up Ben's circuit by adding buffers to slow down the short paths, as shown in Figure 3.44. The buffers take the same delays as other gates. Aid her determine the maximum clock frequency and whether any hold time issues could occur.

Figure 3.44. Corrected circuit to fix hold time problem

Solution

Figure three.45 shows waveforms illustrating when the signals might change. The critical path from A to Y is unaffected considering information technology does not pass through any buffers. Therefore, the maximum clock frequency is still four   GHz. Notwithstanding, the short paths are slowed by the contamination filibuster of the buffer. Now, X′ will non change until t _ccq + 2t _cd = 30 + 2 × 25 = 80 ps. This is after the lx ps agree time has elapsed, and then the circuit now operates correctly.

Effigy 3.45. Timing diagram with buffers to gear up concord time problem

This example had an unusually long concur time to illustrate the bespeak of hold time problems. Most flip-flops are designed with t _hold < t _ccq to avoid such problems. Nevertheless, some high-functioning microprocessors, including the Pentium 4, use an chemical element called a pulsed latch in place of a flip-flop. The pulsed latch behaves similar a flip-flop only has a brusk clock-to-Q delay and a long hold time. In general, adding buffers can usually, merely not ever, solve hold time issues without slowing the critical path.

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Device- and Circuit-Level Modeling, Measurement, and Mitigation

In Architecture Design for Soft Errors, 2008

Modeling the Furnishings of Masking in Logic

When a particle strikes a sensitive node of a excursion, it produces a current pulse with a rapid rise time simply a more than gradual fall time. Hence, the starting time footstep in modeling the masking effects is to model this current pulse I(t) equally a time-dependent current source [6, 28]:

where Q is the amount of accuse nerveless from a particle strike and the time constant T is a function of the CMOS process. A smaller T results in a shorter, just more than intense, pulse compared to the pulse produced by a larger T. The foursquare root function captures the rapid rise in the electric current pulse, whereas the negative exponential term captures the gradual autumn of the pulse. Typically, both T and Q decrease with each successive technology generation.

This current pulse tin can at present be used to drive circuit simulators, such as SPICE, to estimate the touch of a particle strike on a logic gate.

Logical Masking Conceptually, computing the effect of logical masking is relatively straightforward. It involves injecting erroneous electric current pulses into different parts of a logic cake and simulating its operation for various inputs or benchmarks. A random sample of nodes and pulses is typically selected to avoid simulating the logic block under every different configuration of inputs and mistake pulses. Alternatively, logical masking tin also be modeled in a logic-level simulator past flipping inputs from zero to one or vice versa. The latter method is much faster because it does not involve detailed simulation of a current pulse and its effect on the logic.

Electric Masking Calculating the effects of electric and latch-window masking is a little more than involved. As the current pulse traverses through the cascade of gates, its force continues to attenuate. More specifically, the rise and fall times of the pulse increase and its aamplitude decreases. The increase in rising and fall times of the pulse results from circuit delays caused by the switching delay of the transistors. The subtract in amplitude may occur if and when a gate turns off before the output pulse reaches its full amplitude. This can happen if an input transition occurs earlier the gate has completely switched from its previous transition. This causes the gate to switch in the contrary direction before reaching the elevation amplitude of the input pulse, thereby degrading the output pulse. This consequence cascades from i gate to the next, thereby slowly attenuating the signal. If the signal completely attenuates earlier reaching the frontwards latch, then the forward latch does non record an erroneous value, and the error is said to be electrically masked. Shivakumar et al. [25] used the rise and fall time model of Horowitz [12] and the logical delay degradation model of Bellido-Diaz et al. [2] to compute the touch on of electric masking through a logic block.

Latch-Window Masking An edge-triggered latch is only vulnerable to latching in a propagated error during a small latching window around its closing clock edge (Figure 2.8). This latching window is effectively the sum of the setup time and agree time of the latch. The setup fourth dimension is the minimum corporeality of time before the clock edge for which data to be latched in must exist valid. The hold time is the minimum amount of fourth dimension after the clock edge that the data must be valid for the latch to correctly read it in. Pulses that completely overlap the latching window will always crusade an fault in the latch. Pulses that are not overlapped with the latching window will ever exist masked. Pulses that partially overlap with the latching window may or may not be masked. Shivakumar et al. [25] believe that errors caused past partially overlapped pulses are a secondary result.

FIGURE 2.8. Latch-window masking.

Presume c = clock cycle, d = pulse width, and westward = width of latch window. If soft errors due to partially overlapped pulses are ignored, and so the probability of a soft error tin exist expressed as

▪

If d < w, Probability(soft error) = 0 because the pulse cannot span the entire latch window.

▪

If w ≤ d ≤ c + westward, Probability(soft error) = (d – west)/c because the pulse must make it in the interval (d – westward) just prior to the latching window.

▪

If d > c + west, Probability(soft error) = i, the pulse is guaranteed to overlap with at to the lowest degree one latching window. It should be noted if c < d < c + w, so d can overlap with ii consecutive latching windows and still not cause a soft mistake.

It should be noted that the latch-window masking reduces the error charge per unit of logic gates. In dissimilarity, a strike to a latch may get masked if the latch drives data to its output. This reduces the TVF of the latch. This latter masking effect reduces the mistake charge per unit of the latch and not the fault rate of the logic gates feeding information technology.

Putting All These Together To appropriately model the SER of combinatorial logic gates, all the three masking effects must be taken into account. A fully exhaustive model would simulate accuse collections of all unlike magnitudes and at different nodes of the logic circuits (e.g., every bit in the TIme DEpendent Ser Tool called TIDEST [23]) and and so written report the masking effects for each of these cases. A fully exhaustive simulation model can exist very precise merely can besides lead to extremely long simulation times even for small circuits. Hence, sampling methods, such equally Monte Carlo simulations, are typically used to reduce the simulation space.

Zhang and Shanbhag [28] proposed an alternate approximation to reduce the simulation times required to compute the masking effects. In this method, logical masking effects were computed using error injection into a logic-level simulator, which is significantly faster than a circuit simulator. And then, the electrical and latch-window masking effects were computed using a circuit simulator. For each circuit encountered in a bit, they beginning extracted the path that the resulting fault from a particle strike would propagate through. They mapped this path to an equivalent chain of inverters. The electrical masking and latch-window masking effects were computed ahead of fourth dimension for representative inverter chains. Hence, the effects of electrical and latch-window masking in these circuits become simply a table lookup. The authors plant that this approximation introduced less than 5% error in the SER prediction compared to Monte Carlo-based simulation approaches. Overall, these 3 techniques—using logic-level simulation for logic masking, extracting the path the error propagates through, and mapping the path to an equivalent inverter chain—speed up the masking simulations past orders of magnitude over using brute-force excursion simulation. Other researchers (e.thousand., Gill et al. [7]) are exploring other options to further reduce this simulation time.

Affect of Technology Scaling Equally characteristic size decreases, the relative contribution of logic soft errors may continue to increase. This is because of 3 reasons. First, logic gates are typically wider devices than memory circuits, such every bit SRAM cells. But technology scaling more speedily decreases the size and Qcrit of logic gates than that of SRAM cells.

Second, the effect of electrical masking will decrease with technology scaling. This is because fewer error pulses will benumb as the frequency of these gates continues to increment.

3rd, a higher degree of pipelining, if used by high-end microprocessors and chipsets, will subtract the clock cycle without significantly changing the setup time and agree time of latches. Recently, microprocessors have moved toward shallower pipelines to avert excessive ability dissipation and pattern complexity. Nevertheless, afterwards this sharp change toward shallower pipelines, the number of pipeline stages in a processor continues to increment again. This will decrease the corporeality of latch-window masking experienced by a circuit. Overall, Shivakumar et al. [25] predicted that the SER from logic gates rises exponentially. But the jury is all the same out on this issue.

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Processing Elements

Lars Wanhammar , in DSP Integrated Circuits, 1999

11.vi.3 Serial/Parallel Multiplier

Many forms of then-called serial/parallel multipliers are have been proposed [24,37]. In a series/parallel multiplier the multiplicand, ten , arrives bit-serially while the multiplier, a , is applied in a bit-parallel format. Many different schemes for bit-serial multipliers have been proposed. They differ mainly in which gild bit-products are generated and added and in the way subtraction is handled. A common approach is to generate a row, or diagonal, of flake-products in each time slot (see Figure eleven.8) and perform the additions of the bit-products concurrently. We will in this and the following sections describe several alternative serial/parallel multiplier algorithms and their implementations.

First, lets consider the special case when data is positive, ten ≥   0. Here the shift-and-add algorithm tin can exist implemented by the circuit shown in Effigy 11.xiv, which uses comport-save adders. The coefficient give-and-take length is five $.25. Since x is processed bit-serially and coefficient a is processed bit-parallel, this type of multiplier is called a serial/parallel multiplier. Henceforth we practise not explicitly bespeak that the D flip-flops are clocked and reset at the first of a computation.

Figure eleven.xiv. serial/parallel multiplier based on conduct-salve addres

Addition of the first ready of partial bit-products starts with the products corresponding to the LSB of x . Thus, in the offset fourth dimension slot, at bit $x_{{\mathrm{Westward}}_d-1}$ , we simply add $\mathit{a}\cdot x_{W_d-1}$ to the initially cleared accumulator.

Next, the D flip-flops are clocked and the sum-bits from the FAs are shifted one flake to the right, each comport-bit is saved and added to the FA in the same stage, the sign-bit is copied, and one bit of the product is produced at the output of the accumulator. These operations correspond to multiplying the accumulator contents by two^{−   1}. In the following clock wheel the next flake of ten is used to course the next set up of bit-products which are added to the value in the accumulator, and the value in the accumulator is over again divided past 2.

This process continues for Westward _d  − 1 clock cycles, until the sign fleck of 10 , x ₀, is reached, whereupon a subtraction must be washed instead of an addition. At this point, the accumulator has to exist modified to perform this subtraction of the bit-products, a   · ten ₀. We will present an efficient method to perform the subtraction in Example 11.5. Recall that we assumed that the information here are positive. Hence, x ₀  =   0 and the subtraction is not necessary, but a clock bicycle is still required. The highest clock frequency is determined by the propagation time through i AND gate and one full-adder.

During the first W_d clock cycles, the least significant part of the product is computed and the most meaning is stored in the D flip-flops. In the side by side West_c   −   1 clock cycles, zeros are therefore applied to the input so that the most meaning office of the product is shifted out of the multiplier. Hence, the multiplication requires Westward_d   + Due west_c   −   one clock cycles. Two successive multiplications must therefore be separated past Westward_d   + Due west_c   −   1 clock cycles.

Example eleven.half dozen

Prove that subtraction of the bit-products required for the sign-bit in the series/parallel multiplier can be avoided by extending the input by Westward_c   −   one copies of the sign-chip.

Subsequently Due west_d   −   1 clock cycles the well-nigh meaning part of the product is stored in the D flip-flops. In the next W_c clock cycles the sign bit of ten is applied to the multipliers input. This is accomplished by the sign extension-circuit shown in Figure 11.15. The sign extension-circuit consists of a latch that transmits all bits upwards to the sign-bit and thereafter latches the sign-fleck. For simplicity, we presume that W_d =   six bits and W_c =   5 $.25.

Figure xi.fifteen. Serial/parallel multiplier with sign-extension circuit

The product is

$\mathit{y}\mathit{=}\mathit{a}\cdot \mathit{x}\mathit{=}\mathit{a}\cdot \left\{-x_{\mathit{0}}+{\displaystyle \sum _{i=1}^{\mathrm{five}}{x}_i{2}^{-i}}\right\}$

simply the multiplier computes

(xi.24) $\begin{array}{lll}{y}_{\mathit{Mult}}& =& \mathit{a}\cdot \left\{x_0{\mathrm{two}}^4+{\mathrm{10}}_0{\mathrm{two}}^3+{\mathrm{ten}}_0{\mathrm{two}}^2+{\mathrm{ten}}_0{\mathrm{ii}}^{\mathrm{ane}}+x_0{\mathrm{two}}^0+{\displaystyle \sum _{i=1}^5{x}_i{2}^{-i}}\right\}\\ & =& \mathit{a}\cdot \left\{{\mathrm{10}}_0{2}^{\mathrm{four}}+{\mathrm{ten}}_0{2}^{\mathrm{three}}+x_0{\mathrm{ii}}^2+x_0{2}^1+x_0{2}^1+{\displaystyle \sum _{i=1}^5{x}_i{\mathrm{ii}}^{-i}}\right\}\\ & =& \mathit{a}\cdot {\mathit{ten}}_0\left\{2^4+{\mathrm{two}}^3+2^2+2^{\mathrm{ane}}+2^{\mathrm{i}}\right\}+\mathit{a}\cdot \mathit{ten}\\ & =& \mathit{a}\cdot x_0{2}^5+\mathit{a}\cdot \mathit{x}\end{array}$

The first term here contributes an error in the desired production. However, as shown adjacent, there volition not be an error in the Due west_d   + Due west_c   −   1 least-significant $.25 since the error term only contributes to the bit positions with higher significance.

A scrap-serial multiplication takes at to the lowest degree W_d   + West_c   −   1 clock cycles. In section 11.xv, we will present a technique that uses partially overlapping of subsequent multiplications to increase the throughput. These serial/parallel multipliers, using this technique, tin be designed to perform one multiplication every max{W_d , W_c } clock cycles. A xvi-bit serial/parallel multiplier implemented using ii-phase logic in a 0.eight-μm CMOS process requires an expanse of merely 90   μm   ×   550   μm   ≈   0.050   mm^two.

An culling solution to copying the sign-bit in the first multiplier stage is shown in Figure 11.16. The first stage, corresponding to the sign-chip in the coefficient, is replaced by a subtractor. In fact, only a half-adder is needed since one of the inputs is zero. Nosotros will later on see that this version is often the about favorable ane.

Figure 11.16. Modified serial/parallel multiplier

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Multiplication and Squaring

Tom St Denis , Greg Rose , in BigNum Math, 2006

five.2.4 Polynomial Basis Multiplication

To suspension the O(n ^two) bulwark in multiplication requires a completely different expect at integer multiplication. In the post-obit algorithms the utilize of polynomial ground representation for two integers a and b as $f\left(x\right)=\sum _{i=0}^{\mathrm{due\; north}}{a}_i{\mathrm{ten}}^i$ and $\mathrm{yard}\left(\mathrm{ten}\right)=\sum _{i=0}^{\mathrm{northward}}{b}_i{\mathrm{10}}^i,$ respectively, is required. In this system, both f(x) and g(x) take n+ 1 terms and are of the n′thursday caste.

The product a. b≡ f(x)g(ten) is the polynomial $W\left(x\right)={\displaystyle {\sum }_{i=0}^{2n}{\mathrm{due\; west}}_i{\mathrm{ten}}^i}$ . The coefficients w _i will directly yield the desired product when β is substituted for ten. The direct solution to solve for the 2due north+ 1 coefficients requires O(north ⁱⁱ) fourth dimension and would in practice be slower than the Comba technique.

Still, numerical analysis theory indicates that only 2n+ ane distinct points in W(x) are required to determine the values of the twodue north+one unknown coefficients. This means by finding ζ _y = Westward(y) for 2n+ 1 pocket-size values of y, the coefficients of Due west(x) can exist establish with Gaussian elimination. This technique is too occasionally referred to equally the interpolation technique [5], since in issue an interpolation based on twon+ ane points volition yield a polynomial equivalent to W(x).

The coefficients of the polynomial Due west(x) are unknown, which makes finding W(y) for any value of y impossible. Yet, since W(ten) = f(ten)g(ten), the equivalent ζ _y = f(y)g(y) tin be used in its place. The benefit of this technique stems from the fact that f(y) and g(y) are much smaller than either a or b, respectively. As a upshot, finding the 2n+ 1 relations required past multiplying f(y)g(y) involves multiplying integers that are much smaller than either of the inputs.

When you lot are picking points to gather relations, at that place are always three obvious points to choose, y = 0, ane, and ∞. The ζ₀term is simply the product Westward(0) = west ₀= a ₀. b ₀. The ζ₁term is the product $\mathrm{West}\left(1\right)=\left({\displaystyle {\sum }_{i=0}^{\mathrm{north}}{a}_i}\right)\left({\displaystyle {\sum }_{i=0}^n{b}_i}\right)$ . The third point ζ_∞is less obvious only rather uncomplicated to explicate. The 2north+ 1′thursday coefficient of W(x) is numerically equivalent to the most significant column in an integer multiplication. The bespeak at ∞ is used symbolically to represent the most significant column– Westward(∞) = w _{2due north} = a _northward b _northward . Notation that the points at y = 0 and ∞ yield the coefficients w ₀and w _2n straight.

If more points are required they should exist of modest values and powers of 2such as 2 ^q and the related mirror points(two ^q )ⁱⁱⁿ . ζ_{two– q} for modest values of q. The term "mirror point" stems from the fact that (2 ^q )²ⁿ . ζ_{2– q} can be calculated in the verbal opposite fashion as ζ_twoq . For instance, when n = two and q = one, the following two equations are equivalent to the point ζ_iiand its mirror.

(5.5) $\begin{array}{c}\hfill {\varsigma }_{\mathrm{ii}}=f\left(2\right)g\left(2\right)=\left(\mathrm{iv}{a}_2+2a_1+a_0\right)\left(4b_2+2b_1+b_0\right)\\ \mathrm{sixteen.}{\varsigma }_{\frac{\mathrm{ane}}{2}}=4f\left(\frac{\mathrm{i}}{2}\right).4g\left(\frac{1}{2}\right)=\left(a_2+2a_1+4a_0\right)\left(b_{\mathrm{ii}}+2b_{\mathrm{i}}+4b_0\right)\hfill \end{array}$

Using such points will let the values of f(y) and m(y) to be independently calculated using only left shifts. For case, when n = ii the polynomial f(ii ^q ) is equal to ii ^q ((2 ^q a _ii) + a _i) + a ₀. This technique of polynomial representation is known as Horner's method.

As a full general rule of the algorithm when the inputs are carve up into due north parts each, there are 2n– i multiplications. Each multiplication is of multiplicands that have north times fewer digits than the inputs. The asymptotic running fourth dimension of this algorithm is O(k ^{lgn (2n–1)}) for 1000 digit inputs (assuming they have the same number of digits). Effigy 5.vii summarizes the exponents for various values of northward.

Figure 5.7. Asymptotic Running Time of Polynomial Basis Multiplication

At get-go, it may seem like a expert idea to cull due north = 1000 since the exponent is approximately one · 1. Even so, the overhead of solving for the 2001 terms of W(x) will certainly swallow whatever savings the algorithm could offer for all just exceedingly large numbers.

Cutoff Bespeak

The polynomial basis multiplication algorithms all require fewer single precision multiplications than a direct Comba approach. Nonetheless, the algorithms incur an overhead (at the O(northward)work level) since they require a system of equations to be solved. This makes the polynomial basis approach more costly to apply with modest inputs.

Allow m correspond the number of digits in the multiplicands (assume both multiplicands have the same number of digits). In that location exists a signal y such that when chiliad < y, the polynomial basis algorithms are more costly than Comba; when yard = y, they are roughly the same toll; and when g >y, the Comba methods are slower than the polynomial ground algorithms.

The exact location of y depends on several key architectural elements of the computer platform in question.

1.

The ratio of clock cycles for single precision multiplication versus other simpler operations such equally addition, shifting, etc. For example on the AMD Athlon the ratio is roughly 17 : i, while on the Intel P4 it is 29 : 1. The higher the ratio in favor of multiplication, the lower the cutoff betoken y volition be.

2.

The complexity of the linear system of equations (for the coefficients of Due west(10)) is, generally speaking, as the number of splits grows the complexity grows essentially. Ideally, solving the system will only involve addition, subtraction, and shifting of integers. This directly reflects on the ratio previously mentioned.

3.

To a lesser extent, memory bandwidth and function call overhead affect the location of y. Provided the values and code are in the processor cache, this is less of an influence over the cutoff point.

A make clean cutoff signal separation occurs when a point y is constitute such that all the cutoff signal conditions are met. For example, if the point is too low, there will exist values of m such that m> y and the Comba method is still faster. Finding the cutoff points is fairly unproblematic when a high-resolution timer is available.

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CPUs

Marilyn Wolf , in High-Performance Embedded Calculating (Second Edition), 2014

two.4.2 Superscalar processors

Superscalar processors upshot more than one teaching per clock cycle. Unlike VLIW processors, they bank check for resource conflicts on the wing to determine what combinations of instructions tin can be issued at each stride. Superscalar architectures dominate desktop and server architectures. Superscalar processors are not as mutual in the embedded world every bit in the desktop/server globe. Embedded computing architectures are more than likely to be judged past metrics such equally operations per watt rather than raw performance.

A surprising number of embedded processors do, however, brand apply of superscalar instruction issue, though non every bit aggressively every bit do high-end servers. The embedded Pentium processor is a two-issue, in-lodge processor. It has 2 pipes: i for whatsoever integer performance and another for unproblematic integer operations. We saw in Section 2.three.1 that other embedded processors also use superscalar techniques.

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Advances in Computers

Amjad Ali , Khalid Saifullah Syed , in Advances in Computers, 2013

8.2 Exploitation of Locality of Reference

Information technology is well recognized that the number of CPU clock cycles required for a typical principal memory access is much larger (sometimes more than than 30 times larger) than the number of CPU clock cycle required for any floating point arithmetic performance (fifty-fifty for the square root and transcendental function evaluation to some extent) [33, 34]. An elegant approach for developing efficient programs is to write the source code so equally to make efficient utilization of the multilevel cache memory arrangement (normally available in the mod CPUs). As mentioned earlier, the multilevel cache systems in modern CPUs provide for exploitation of the phenomenon of the locality of reference. This also necessitates the programmer to understand the retentivity system (i.e., when the information retain in the caches) and memory access pattern of the program. Thus, the programmer tin restructure the lawmaking to enhance the locality of reference so that the code attempts for caching the data in the mode that a very big number of information accesses is satisfied from the caches and a very small-scale number of data accesses is needed to exist satisfied from the chief memory [34]. For example, two approaches that enhance the locality of reference are as follows. (1) All the loops on the multidimensional arrays should exist traversed such that the club of accessing the array elements matches with the club of the storage in the memory. Call back that Fortran stores the array elements with column-major order whereas C, C++, and Coffee shop the array element with row-major order. (ii) Keeping lesser number of arrays (and data sizes in general) in utilize might reduce the cache foot-print, as well. The cache human foot-print of a code segment at a certain moment refers to the corporeality of working space it requires at that moment during the execution of the code segment. Conspicuously, more the number of arrays or information structures in utilize, larger would be the cache foot-print. Smaller cache foot-print sizes take greater probability of getting fitted into the enshroud and speedup the execution.

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CPUs

Marilyn Wolf , in Computers as Components (Fourth Edition), 2017

Interrupts in C55x

Interrupts in the C55x [Tex04] have at least seven clock cycles. In many situations, they take 13 clock cycles.

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A maskable interrupt is processed in several steps one time the interrupt request is sent to the CPU.

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The interrupt flag register (IFR) corresponding to the interrupt is set.

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The interrupt enable register (IER) is checked to ensure that the interrupt is enabled.

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The interrupt mask register (INTM) is checked to be sure that the interrupt is not masked.

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The interrupt flag register (IFR) corresponding to the flag is cleared.

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Appropriate registers are saved equally context.

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INTM is set up to ane to disable maskable interrupts.

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DGBM is set to i to disable debug events.

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EALLOW is gear up to 0 to disable access to non-CPU emulation registers.

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A branch is performed to the interrupt service routine (ISR).

The C55x provides two mechanisms—fast-return and wearisome-render—to save and restore registers for interrupts and other context switches. Both processes salve the return accost and loop context registers. The fast-return mode uses RETA to salve the return address and CFCT for the loop context bits. The slow-return manner, in contrast, saves the return address and loop context bits on the stack.

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Profiling and timing

Jim Jeffers , ... Avinash Sodani , in Intel Xeon Phi Processor High Performance Programming (2nd Edition), 2016

Time Stamp Counter

Each core has a 64-bit TSC that is incremented every reference clock bike (the counter is at a fixed frequency regardless of the actual CPU frequency). The values of TSC on each core are synchronized, so it is possible to compare TSC values generated past different cores (due east.g., if yous want to know if one result happened earlier another in a parallel program). TSC can even be used to measure wall-clock time by dividing by the reference frequency; however, if authentic wall-clock time is needed, especially over a long interval,  gettimeofday (2) should be used instead.

The Read Time-Stamp Counter instruction  RDTSC loads the content of the cadre's fourth dimension-stamp counter into the  EDX:EAX registers. The Intel C/C++ compiler supports the _rdtsc() intrinsic to return an unsigned long containing the TSC value. The TSC teaching takes approximately 30 clock cycles (25  ns at 1200   MHz). Getting access to the __rdtsc() intrinsic from Fortran is done via utilize of phone call the C function equally shown in Fig. 14.nineteen.

Fig. 14.19. Calling __rdtsc from Fortran.

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Fault Tolerance in Computer Systems—From Circuits to Algorithms*

Shantanu Dutt , ... Fran Hanchek , in The Electrical Engineering Handbook, 2005

8.5.1 Support for Microrollback in the Register File

In a RISC processor, a write into a annals may be performed every clock cycle. Incremental checkpointing is performed for the register file by using a delayed-write buffer (DWB) to store the written register values for up to N clock cycles to realize a rollback range of N. Figure 8.16 shows the DWB structure for supporting microrollback in the register file.

Effigy viii.16. A Register File with Support for Microrollback

The accost of the destination annals and its new value are stored in the DWB, which is an N-level FIFO buffer. This storage structure is composed of an N-level information FIFO that contains the values of the registers that have been written and an N-level content associative retentivity (CAM) that stores the addresses of the written registers plus valid $.25 for the data FIFO entries. In each clock bike, if a write register operation is executed, a new line of the DWB is filled; otherwise, the line is invalidated by resetting the corresponding valid flake in the CAM. This microrollback structure too accommodates the needed alter in the read of the annals file so that the latest value of the addressed annals is read. During a read, the DWB checks the CAM to determine if the addressed register's content is stored in its data shop. If so, a priority circuit chooses the nigh contempo written value of the addressed register to be read out of the information FIFO. A microrollback of d clock cycles is implemented simply by invalidating the first (most recent) d locations of the DWB.

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Digit-Serial Arithmetics

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

9.1.1 Modes of Performance and Algorithm and Implementation Models

We consider the case in which the numerical values are represented in a radix-r number organisation. In some cases, we utilize conventional representations, while in others redundant representations are preferable.

A series signal is a numerical input or output with i digit per clock cycle. Figure 9.1 shows typical timing diagrams for a serial operation, in which in each bike 1 digit of each operand is applied and one digit of the output is delivered. Note that by convention nosotros denote as cycle 1 the cycle in which the first digit of the output is delivered. The total execution time is the sum of two components:

Effigy 9.1. Timing characteristics of serial operation with n = 12. (a) With δ = 0. (b) With δ = 3.

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The initial delay δ, which corresponds to the boosted number of operand digits required to determine the first effect digit. That is, the first output digit is delivered δ + 1 cycles after the application of the beginning input digits. Then, as shown in Figure 9.ane(a), δ = 0 corresponds to the example in which the showtime output digit is delivered i cycle after the application of the beginning input digits. Figure nine.i(b) shows a instance in which the get-go output is delivered in the cycle after four input digits have been practical (δ = 3).

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The time to deliver the due north output digits. Since one digit is delivered per bike, for an output of n digits, this time is equal to due north cycles.

Consequently, the execution fourth dimension is

9.1 $T_n+\delta +1+\mathrm{northward}$

Serial Modes

Ii serial modes are typical:

1.

Least-significant digit first (LSDF) mode. The digits of the operands (result) are applied serially starting from the least-significant digit. This manner is too known as correct-to-left mode and, since it was the starting time series manner, typically this mode is implied when the term 'series arithmetic' is used.

Because of the order of the digits, the indexing is simplified if right-to-left indexing is used, equally in the representation of integers, namely,

9.ii $\mathrm{ten}+{\displaystyle \sum _{i=0}^{n-1}{x}_i{r}^i}$

2.

Most-significant digit beginning (MSDF) mode. The digits are practical starting from the most-significant digit (left-to-right fashion). Arithmetics performed in this mode is known every bit online arithmetic, and the respective initial delay is called online delay.

The indexing is simplified here by using left-to-correct indexing, as in the representation of fractions, that is,

9.3 $x+{\displaystyle \sum _{i=\mathrm{ane}}^n{x}_i{r}^{-i}}$

Algorithm and Implementation Model

We now draw a general model for a series algorithm and its implementation. Consider an operation with two due north radix-r digit operands, x and y, and ane upshot z. The input-output model is described as follows.

In cycle j the result digit z _j+1 is computed. Consequently the cycles are labeled from −δ, …, 0, 1, …, n so that in bicycle j the operand digits x _j+1 and y _j+1+δ are received, output digit z _j+1 is computed, and output digit z_j is delivered (Figure 9.two(a)). To arrange with both serial modes, in LSDF (MSDF) way digits are counted from the least-significant (near-meaning) side.

FIGURE 9.2. Serial algorithm model: (a) Timing. (b) Implementation.

The algorithm consists of recurrences on numerical values. In each of the n + δ iterations, one digit of the operands is introduced (for the final δ iterations the input digits are prepare to aught), an internal state w (too called a balance) is updated, and 1 digit of the outcome is produced (zero for the outset δ cycles). ² An additional cycle is needed to evangelize the last consequence digit.

Calling x[j],y[j], and z[j] the numerical values of the corresponding signals when the representation consists of the first j + δ digits for the operands and j digits for the result, iteration j is described by

9.four $\begin{array}{ll}\mathrm{ten}\left[j+\mathrm{one}\right]\hfill & =\left(x\left[j\right],x_{j+1+\delta }\right)\hfill \\ y\left[j+\mathrm{one}\right]\hfill & =\left(y\left[j\right],y_{j+1+\delta }\right)\hfill \\ \hfill z_{j+1}& =F\left(w\left[j\right],x\left[j\right],x_{j+\mathrm{ane}+\delta },y\left[j\right],y_{j+1+\delta },z\left[j\right]\right)\hfill \\ z\left[j+1\right]\hfill & =\left(z\left[j\right],z_{j+1}\right)\hfill \\ \mathrm{westward}\left[j+1\right]\hfill & =\mathrm{Thousand}\left(\mathrm{due\; west}\left[j\right],x\left[j\right],{\mathrm{10}}_{j+\mathrm{ane}+\delta },y\left[j\right],y_{j+1+\delta },z\left[j\right],z_{j+1}\right)\hfill \end{array}$

Effigy 9.2(b) depicts the serial algorithm and implementation model.

The initial delay δ depends on the series mode and on the specific functioning (Table 9.1). As can be seen from the table, for the MSDF mode all bones operations can be performed with a small and stock-still (independent of the precision) initial filibuster. On the other hand, for the LSDF mode, but addition and multiplication have a small initial delay, whereas sectionalization, square root, and max/min have an initial delay O (n), which means that this fashion is not suitable for these operations. Moreover, the initial delay is also O (n) for multiplication if only the near-significant half of the production is required (come across Figure 9.3(a)).

Tabular array nine.1. Initial delay (δ).

Operation	LSDF	MSDF
Improver	0	2 (r = 2)
		1 (r ≥ 4)
Multiplication	0	3 (r = ii)
		two (r = 4)
Simply MS half of product	n
Partitioning	2n *	4
Foursquare root	twon *	iv
Max/min	northward	0

*

The issue digits delivered LS start.

Figure 9.3. (a) LSDF and (b) MSDF modes.

Equally seen in Figure 9.3(b), online arithmetic is well-suited for variable precision computations: once a desired precision is obtained, the performance tin terminate.

Blended Algorithm

Since the execution time of a serial operation can exist high, it is convenient to develop composite algorithms in which the execution of successive (dependent) operations overlap; that is, a successor operation can begin equally soon equally the result digits of its predecessors are available. This is illustrated in the following example where a sequence of operations is implemented by a network of digit-serial (online) arithmetic modules. The network in Figure 9.4(a) implements the expressions for the 2d vector normalization. ^three

FIGURE 9.4. Online computation in 2D vector normalization: (a) Network. (b) Timing diagram.

9.five $\begin{array}{ll}c=\frac{x}{\sqrt{x^2+y^2}}\hfill & \mathrm{southward}=\frac{y}{\sqrt{{\mathrm{ten}}^{\mathrm{ii}}+y^2}}\hfill \end{array}$

The corresponding timing diagram is given in Figure 9.four(b).

The online filibuster of the network is the sum of online delays of the operations on the longest path. For r = 2, we obtain from Table nine.1

9.half dozen ${\Delta }_{\mathrm{north}or\mathrm{one\; thousand}}=\delta \mathrm{ane}+\delta 2+\delta 3+\delta 4=3+\mathrm{ii}+4+\mathrm{iv}=13$

The total execution time for the composite operation is D_norm = δ_norm + 4 + due north.

The more than levels there are in a sequence of operations and the longer the precision, the more advantageous is the online approach.

To reduce further the execution time, the three modules in the dashed box in Figure 9.four(a) tin be merged into a single online module, called a composite module, with a shorter online delay than the sum of the online delays of the dependent components.

The latency in the case of LSDF arithmetic is obtained in a similar manner (Exercise 9.1).

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